The present invention relates to a display device, and more particularly to a technique which is effectively applicable to a drive circuit of a liquid crystal display device used in a mobile phone or the like.
A TFT-method liquid crystal display module having a small liquid crystal panel with approximately 240×320×3 sub pixels in color display has been popularly used as a display part of a portable digital assistant (PDA) such as a mobile phone.
With respect to the liquid crystal display module which is used as the display part of the mobile phone or the like, to reduce the power consumption, there has been known a liquid crystal display module which includes a semiconductor memory (Static Random Access Memory: hereinafter referred to as SRAM).
FIG. 27 is a circuit diagram showing one memory cell of a conventional SRAM.
As shown in the drawing, one memory cell of the conventional SRAM is constituted of a word line (W), a data line (DT, DB), N-type MOS transistors (hereinafter simply referred to as NMOS) (M1, M2) which constitute transfer switching elements, and inverters (I1, I2).
In FIG. 27, node 1 and node 2 express internal nodes.
Further, sizes of the respective NMOS (M1, M2) are adjusted such that when a level value between the data line DT which is connected with the NMOS (M1) and the inner node (node1) and a level value between the data line DB which is connected with the NMOS (M2) and the inner node (node2) differ from each other, the node on a High-level (hereinafter called H-level) side node is changed to a Low-level (hereinafter called L-level).
That is, since the writing/reading of the L level is possible, the manner of operation of the SRAM cell shown in FIG. 27 is described as follows.
(1) Writing Operation
Before setting the word line W to the H level, the precharging is performed so as to make the data lines (DT, DB) assume a power-source voltage Vcc temporarily.
Next, the word line W is set to the H-level to turn on the NMOS (M1, M2). At this point of time, since the data lines (DT, DB) assume the H-level, the values of the internal nodes are not changed and the data of a RAM is held.
Next, only the data line of the SRAM by which the writing is performed is changed. For example, in case of writing “0”, by setting the data line (DT) to the L-level, the internal node (node1) surely assumes the L level and “0” is written. On the other hand, in case of writing “1”, only the data line (DB) is set to an L-level after precharging. Then, the internal node (node2) surely assumes the L level and the internal node (node1) assumes the H-level due to an inverter (I2). “1” is written in the SRAM.
(2) Reading Operation
Before setting the word line W to the H level, the precharging is performed so as to make the data lines (DT, DB) assume a power-source voltage Vcc temporarily.
Next, the word line W is set to the H-level to turn on the NMOS (M1, M2). Then, when the data stored in a memory cell is “0”, since the internal node (node1) is at the L-level, only the data line (DT) is changed to the L-level.
On the other hand, when the data stored in a memory cell is “1”, since the internal node (node2) is at the L-level, only the data line (DB) is changed to the L-level. Accordingly, the reading operation of the data of the SRAM is performed.
It is needless to say that, to perform the above-mentioned operations, sizes of transistors in the inside of the respective inverters are adjusted.
As the related art literatures relevant to the present invention, US2004/066363A1 (literature 1), US2001/0052887A1 (literature 2), Japanese Patent Laid-open No. 318566/2002 (literature 3), Japanese Patent Laid-open No. 84722/2003 (literature 4) and Japanese Patent Laid-open No. Hei11/134866 (literature 5) are named.